The Chapel programming language recently added support for the RISC-V architecture. Here we discuss what changes were needed for Chapel to work on RISC-V as well as lessons learned from the porting process. We use some of Chapel's extensive benchmark suite to gain further insight into the suitability of the RISC-V architecture for future HPC use. We compare performance on SiFive P550 and Unmatched
Porting Chapel to RISC-V was determined to be a moderate challenge for the well-maintained codebase, requiring minimal build system changes and primarily relying on C11 atomics to minimize platform-specific assembly. The only significant code modification involved adding a RISC-V assembly implementation for fast context swaps within the Qthreads runtime, which handles thread scheduling.
Benchmarking results from SiFive P550, Unmatched, and Sophon SG2042 boards indicate that while current RISC-V hardware is not yet competitive with state-of-the-art x86 and ARM server-class systems, it performs as expected for its cost and power profile. The study highlights that while adding initial ISA support is tractable, there is an urgent need for improved performance portability to maintain efficiency across the diverse hardware configurations enabled by RISC-V’s extensible ISA.
Key lessons include: Dependency Barriers: Lack of binary packages for libraries like LLVM and GPU runtimes currently limits distributed and GPU-based execution support. Allocator Choice: Jemalloc does not support RISC-V, necessitating the use of Mimalloc for parallel memory allocation. * Future Viability: The upcoming RVA23 profile and server-class RISC-V chips are expected to significantly improve software stack setup and HPC competitiveness.
This paper examines the porting of the Chapel HPC programming language to the RISC-V architecture and uses the resulting implementation to evaluate how well current RISC-V hardware supports Chapel-style parallel workloads. It describes the changes required across Chapel’s compiler, runtime, and build system to make the language functional on RISC-V, including handling architecture-specific code generation, platform assumptions, and low-level runtime behavior. The porting process is presented as a case study in how a mature HPC language can be adapted to an open, less mature ISA, with lessons learned about the kinds of hidden architecture dependencies that can surface when extending a compiler and runtime to a new platform.
The second major contribution is a benchmark-based assessment of RISC-V’s suitability for future HPC use. The authors use a subset of Chapel’s benchmark suite to compare performance on the SiFive P550 and an Unmatched system, using Chapel’s high-level parallel constructs to exercise patterns common in scientific computing. Rather than focusing only on raw microarchitectural metrics, the study evaluates how the language, compiler, runtime, and hardware interact on representative workloads. This approach helps distinguish whether observed performance limitations stem from RISC-V implementation details, compiler support, runtime behavior, or the broader hardware platform.
The work matters because it sits at the intersection of HPC software portability, compiler engineering, and emerging open-architecture hardware. Chapel is a serious parallel programming language for high-performance computing, and RISC-V is increasingly relevant as an open ISA for both specialized accelerators and general-purpose HPC systems. By documenting both the porting effort and the performance implications, the paper provides useful evidence for RISC-V vendors, compiler developers, and HPC researchers about what is needed to make RISC-V a practical target for production scientific workloads.