The sparse matrix-vector multiplication (SpMV) algorithm is a fundamental computational kernel of linear algebra and serves as a building block for numerous applications, primarily iterative solvers for systems of linear equations used in scientific and engineering simulations. This paper compares vectorized implementations of the SpMV algorithm across eight established sparse matrix storage forma
Recent research highlights that RISC-V processors with SIMD units (RVV 1.0) can significantly accelerate SpMV by leveraging vector-friendly storage formats such as SELL-p and JDS (Jagged Diagonal Storage). These formats mitigate the memory-bound nature of SpMV by ensuring aligned memory access patterns and reducing cache misses compared to traditional CSR layouts.
On commercial RISC-V platforms, SELL-p provides the highest overall acceleration, while JDS offers comparable performance with a reduced memory footprint. For structured-sparse matrices, implementing custom instructions like vindexmac further enhances performance by optimizing data locality and reducing instruction overhead in vector register files.
The paper revisits sparse matrix-vector multiplication (SpMV) on RISC-V by treating the sparse storage format as a first-class performance design variable rather than an implementation detail. It compares vectorized SpMV kernels across eight established sparse matrix storage formats, examining how each format interacts with RISC-V vector execution, memory access patterns, cache behavior, and the inherent irregularity of sparse data. The central motivation is that format rankings developed for scalar CPUs or other vector architectures may not transfer cleanly to RISC-V, where vector length, tail handling, register pressure, and memory-system constraints can change the relative advantages of compact, regular, or block-oriented layouts.
A key contribution is a hierarchical approach to SpMV that aims to preserve the storage efficiency of conventional sparse formats while improving vector utilization and memory locality. Instead of relying on a single flat representation, the approach organizes sparse data in a way that exposes more regular, vector-friendly substructures, reducing the cost of irregular gathers/scatters and better aligning work with the RISC-V vector unit. The paper’s insight is that high-performance SpMV on modern RISC-V systems may require a compromise between compression, vectorization, and hierarchy: formats that look suboptimal in scalar or classical vector settings can become competitive, or even superior, when their structural regularity is exploited by vectorized hierarchical kernels.
This work matters because SpMV is a foundational kernel for iterative solvers, scientific simulation, machine learning, and graph-structured computation. As RISC-V moves into high-performance computing, embedded systems, and energy-efficient accelerators, efficient sparse linear algebra will be essential to realizing its potential. The study provides practical guidance for library developers, compiler/runtime designers, and application engineers on how sparse format choice and kernel design should be co-optimized for RISC-V vector architectures, rather than assuming that one canonical format will dominate across all workloads and platforms.